The interconnection of control units, sensor systems, and actuator systems by use of a network or communication system composed of a communication connection, in particular a bus, and corresponding communication components has greatly increased in recent years in the construction of modern motor vehicles, as well as in mechanical engineering, in particular in the area of machine tools, and also in automation. It is possible to achieve synergetic effects by distributing functions over multiple users, in particular control units. These are referred to as distributed systems. Such distributed systems or networks are thus composed of the users and the bus system or multiple bus systems connecting these users. Thus, there is increasingly more communication between various stations or users via such a communication system, bus system, or network, via which the data to be transmitted are conveyed in messages. This communications traffic on the bus system and access and reception mechanisms, as well as error processing, are controlled using a corresponding protocol, the name of the particular protocol (in the present case as well) frequently being used as a synonym for the networks or bus systems themselves.
The controller area network (CAN) bus, for example, has become established as a protocol in the automotive industry. This is an event-controlled protocol; i.e., protocol activities such as transmission of a message are initiated by events which originate outside the communication system. Unambiguous access to the communication system or bus system is achieved via priority-based bit arbitration. A prerequisite is that a priority be assigned to the data to be transmitted, and therefore, to each message. The CAN protocol is very flexible; thus, it is very easy to add additional users and messages, provided that free priorities (message identifiers) are available. The collection of all messages to be transmitted in the network, together with priorities and their transmitting or receiving users or the corresponding communication components, are stored in a list, the so-called communication matrix.
An alternative approach to event-controlled, spontaneous communication is an approach that is a strictly time-controlled approach. All communication activities on the bus are strictly periodic. Protocol activities such as the transmission of a message are triggered only by updating a time period that is valid for the entire bus system. Access to this medium is based on the allocation of time ranges in which a transmitter has an exclusive transmitting right. The message sequence is generally established before startup. Thus, a schedule is generated which meets the requirements for messages with regard to repetition rate, redundancy, deadlines, etc. This is referred to as a so-called bus schedule. TTP/C, for example, is such a bus system.
A combination of the advantages of both referenced types of buses is achieved in the approach of the time-controlled CAN, the so-called time-triggered controller area network (TTCAN). TTCAN meets the above-described requirements for time-controlled communication as well as the requirements for a certain degree of flexibility. TTCAN meets these requirements by establishing the communication cycle in so-called “exclusive time windows” for periodic messages from specific communication users, and in so-called “arbitrating time windows” for spontaneous messages from multiple communication users. TTCAN is based essentially on time-controlled, periodic communication which is clocked by a primary timing user or communication component, the so-called “time master,” using a time reference message.
Another possibility for combining various types of transmission is offered by the FlexRay protocol, in which a rapid, deterministic, error-tolerant bus system is provided, in particular for use in a motor vehicle. This protocol operates according to the time division multiple access (TDMA) method, the users, i.e., the messages to be transmitted, being assigned fixed time slots in which they have exclusive access to the communication link (the bus). The time slots are repeated in a fixed cycle, so that the point in time at which a message is transmitted over the bus may be predicted precisely, and the bus access is achieved deterministically. To make optimal use of the bandwidth for the transmission of messages on the bus system, the cycle is divided into a static portion and a dynamic portion. The fixed time slots are located in the static portion, at the start of a bus cycle. In the dynamic portion the time slots are dynamically allocated according to the flexible time division multiple access (FTDMA) method. In this process the exclusive bus access is permitted in each case for only a brief period. If there is no access, the access is enabled for the next user. This time period is referred as a “minislot,” in which waiting takes place for access by the first user.
As described above, there are many different transmission technologies and therefore different types of bus systems or networks. It is often necessary to connect multiple systems of the same type or different types. For this purpose a bus interface unit, a so-called gateway, is used. A gateway is thus an interface between various buses which may be of the same type or different types, the gateway relaying (partial) messages from one bus to one or more other buses. Known gateways are composed of multiple independent communication components, the exchange of messages taking place via the processing interface (CPU interface) of the particular user or the corresponding interface component of the particular communication component. This CPU interface is subjected to heavy load on account of this data exchange and other application functions, in addition to the messages to be transmitted to the user itself, so that, together with the resulting transmission structure, this results in a relatively low data transmission speed, or alternatively, a high clock frequency with high power consumption. There are also integrated communication controllers or communication components which share a common message memory, so-called message RAM, in order to compensate for the structural disadvantages. However, such integrated communication components are therefore very inflexible with regard to data transmission, and in particular are fixed on a specified number of bus connections, usually on the same bus system.
FIG. 1 shows a conventional communication component or communication controller CC for a customary gateway, as illustrated in FIG. 2. Communication component CC has an interface for an internal peripheral bus or system bus for the gateway, and has an additional interface for an external serial bus. The system bus includes an address bus, a data bus, and a control bus, and is used for internal data transmission within the gateway. In addition to the communication component, a host CPU having a data memory RAM as well as other optional components, for example DMA controllers, are connected to the system bus. The host CPU is used for internal data processing, and controls the internal data transfer from one communication component CC to another communication component CC. Communication components CC communicate with the host CPU according to the master-slave principle, communication components representing slave units and the host CPU forming a master unit.
As shown in FIG. 1, the internal interface of communication component CC for the system bus is formed by a two-layer interface, namely, a customer interface and a generic interface. The customer interface connects the system bus to the generic interface, the customer interface being manufacturer-specific and easily exchangeable. The generic interface may be connected to a large number of customer-specific system buses via the customer interface. Communication component CC according to the related art, and as illustrated in FIG. 1, also contains buffer memories for temporarily storing data to be transferred. The buffer memories are formed by RAM registers or data registers, for example. Communication component CC also contains a message forwarding unit, i.e., a message handler, for relaying messages from at least one message memory and one communication protocol unit, as well as buffer memories. The message memory or message RAM temporarily stores the message objects to be transferred, in addition to configuration and status information data. The message forwarding unit controls data flow between all buffer memories, the communication protocol unit, and the temporary message memory. Communication protocol unit (PRT) for conventional communication component CC illustrated in FIG. 1 implements communication according to the data transmission protocol used. Communication protocol unit PRT thus performs the transformation or conversion between the data format of data packets DP transmitted via the external serial bus and messages MSG used within the communication component. Messages MSG relayed by the message forwarding unit or message handler are composed of at least one data word DW, the word length, i.e., the bit number, of data word DW preferably corresponding to the bus width of the internally provided data bus for the gateway. If the system bus has an internal data bus that is 32 bits wide, for example, data word DW likewise has 32 bits. A message MSG may be composed of a predetermined number of data words DW. The storage capacity of a buffer memory corresponds, for example, to the data capacity of a message which contains a predetermined number of data words DW. The arbitration of the data flow is performed by the message forwarding unit or message handler.
A number of serial buses and field buses, for example serial field buses such as a CAN bus, FlexRay bus, MOST bus, or LIN bus, are currently used, in particular in vehicles. During operation, data are exchanged between these serial buses, which may form a part of a network, via a gateway GW.
Depending on the vehicle and the functions performed, the data volume in central gateway GW, as illustrated in FIG. 2, may be very high. This data volume results in a high CPU load; i.e., the CPU is burdened with the routing of data from one serial bus to one or more other serial buses. The CPU load is also increased by operations which are necessary for reducing the bandwidth in individual networks or serial buses, for example, combination of the data contents of multiple messages to form a new message.
In many cases it is necessary to periodically send messages in a specified time frame in order to meet safety requirements. For high-priority messages, it may be necessary to immediately transmit the message without time frames, or outside the time frame. Checking whether a message should be retransmitted, or should not be transmitted due to an error such as a missing message, for example, is likewise performed by the CPU for gateway GW, and consumes processing capacity of the CPU.
In many cases the CPU performs additional functions in parallel; i.e., parallel processes run on the CPU which have a mutually adverse effect and delay the transmission or relaying of a message. As a result of these processes running in parallel, “jitter” as well as latency times for transmission of messages increase, since in many cases it is not possible to interrupt the processes running in parallel.